Research of SDPL
With the increasing demand for scaling down semiconductor devices, atomic layer deposition (ALD) has emerged as an essential technology due to its layer-by-layer growth characteristic, which ensures precise thickness control. Additionally, ALD is a highly potent deposition technology due to its excellent uniformity and conformality.
Area-selective atomic layer deposition (AS-ALD) offers the advantage of exploiting surface chemistry to deposit a material in a targeted area. The chemical properties of a surface are controlled to activate or deactivate adsorption of the ALD precursors, so that patterns are formed through selective deposition across differently terminated domains. Therefore, it may allow a reduction in the number of lithography and etch steps, resulting in lower errors in the patterning process as well as a decrease in manufacturing costs.
As the memory devices are more nanoscale and more complex structures for higher capacity and higher density, atomic layer deposition (ALD) is mainly studied, which has relatively better compared to chemical vapor deposition (CVD) in terms of high step coverage, low deposition temperature, and thickness control as atomic level.
Logic devices also require an ALD process with excellent uniformity and conformality to accommodate device scaling and 3D structures. With these advantages, research on ALD processes, such as layering SiO2 and SiN in NAND structures and area-selective ALD (ASALD) processes where growth varies depending on the surface, is being actively pursued.